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EDT 3P Xilinx Virtex 6 FPGA | 10Gbps SFP+



  • Mezzanine board — pairs with an EDT main board (PCIe), which adds DMA, programmable FPGA resources, and memory
  • Port 0: One optional SFP+ for 10GbE (optical), OC192 (STM64), or OTU2/2e/2f at 1550 or 1310 nm (or 10GbE at 850 nm)
  • Port 1: One optional SFP for 1GbE (electrical or optical), OC3/12/48 (STM1/4/16), or OTU1 at 1550, 1310, or 850 nm
  • Port 2: Identical to (but independent of) port 1
    Data processing: SDDS (optional)
  • FPGA: One programmable Xilinx Virtex 6 (XC6VLX240T, LX365T, SX315T, or SX475T)
  • DRAM (DDR2): Three independent 512 MB blocks (or combine two for 1 GB)
  • SERDES: Port 0 = 10G LIU or FPGA MGT; port 1 = SONET/SDH LIU or FPGA MGT; port 2 = SONET/SDH LIU or FPGA MGT
  • EDT intellectual property for 10GbE PCS and PMA layer, SONET/SDH framing, demultiplexing, and G.709 framing
  • Time code input: 1 pps or IRIG-B, with user-configurable output

The 3P is a three-port mezzanine board that pairs with a PCI Express main board to provide three independent channels, each supporting an optional SFP or SFP+. Channel 0 supports up to 10GbE(optical), while channels 1 and 2 each support 1GbE (electrical or optical) or OC3/12/48 (STM1/4/16).

The 3P mezzanine has a user-configurable FPGA (Xilinx Virtex 6 XC6VLX240T, LX365T, or SX315T) that can access three independent 512 MB blocks of DDR2 DRAM, which can be used as data buffers. Two of these can be combined to create a memory block of 1GB.

Each channel links to a SERDES via a specialized LIU or, optionally, via a multi-gigabit transceiver (MGT) in the FPGA. For channel 0, the LIU is 10G; for channels 1 and 2, it is SONET/SDH. Each channel has its own reference clock, programmable from 10 to 210 MHz. A time code input (1 pps or IRIG-B) also is included.

EDT provides FPGA configuration files to support the following: 1GbE and 10GbEdata at the PHY layer (raw, framed, and framed and descrambled); SONET / SDH(raw, framed, framed and descrambled, header, and payload data); and demultiplexing to VC-4C payloads. Custom configuration files can be requested.

The main board supplies DMA, plus additional memory and programmable FPGA resources.

For details on system requirements and EDT-provided software driver packages, see the specifications for the PCIe8 LX main board.

Datasheet 3P

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