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EDT SSE Synchronous serial ECL interface

EDT SSE Synchronous serial ECL interface


  • Mezzanine board — pairs with an EDT PCIe8 LX Main Board, which adds DMA, programmable FPGA resources, and memory
  • Ports 0 and 1 (input) and Port 2 (output): One ECL data bit per port
  • Clocks: Ports 0 and 1 each can receive, and port 2 can generate locally, a clock of up to 300 MHz for Reed-Solomon or 400 MHz for raw serial data
  • FPGAs: One programmable Xilinx Virtex II Pro (XC2VP2 or XC2VP4)
  • Reed-Solomon coding or raw serial data (with frame synchronization or not)
  • Two user-defined LEDs

The SSE is a mezzanine board that pairs with an EDT PCIe8 LX Main Board (for PCI or PCI Express) for high-speed data transfer. It supports three channels (two input and one output) of ECL.

The SSE mezzanine samples the data on the rising edge of the clock and stores it in host memory via the main board. Each channel supports one differential data signal (two wires) and one differential clock (two more wires). Input signals are terminated through 50 ohms to -2 V.

The SSE mezzanine can be custom-configured to support thirty-two additional ECL, LVDS, or RS422 signals in groups of four. The board also can be configured to support one additional signal for applications requiring notification of the start or end of a block transfer.

The PCI SS comes with device drivers and SDK for Windows, and Linux. For details on system requirements and EDT-provided software driver packages, see the specifications for your EDT PCIe8 LX Main Board.

Datasheet SSE Mezzanine

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