The PCIe8 G3 KU-40G is a fast, versatile PCI Express (PCIe, Gen3) x8 interface with one 40G QSFP+ and up to two 10G SFP/+ ports. It supports 1/10/40GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f.
The ports of the PCIe8 G3 KU-40G link to the user-interface (UI) FPGA for serialization / deserialization (SERDES) and clock recovery. Each port has its own reference clock, programmable for 10–210 MHz.
The UI FPGA is a Xilinx Kintex Ultrascale (U035, 060, 085, or 115) with access to two independent 64-bit wide blocks (2 GB each, 4 GB total) of DDR3 DRAM which can act as data buffers. This UI FPGA configures from flash at poweron, and can be reconfigured as many times as desired without powercycling. Up to five images are available, depending on which UI FPGA model is used.
The PCIe FPGA provides up to 16 independent DMA channels via EDT FPGA configuration files.
An optional Lemo supports time code input (1 pps or IRIG‑B), with user-configurable output and two cabling options.
EDT provides FPGA configuration files to support 1GbE and 10GbE at the PHY layer; OC3/12/48/192 and OTU1/2/2e/2f (raw, framed, framed and descrambled); and demultiplexing. Custom files can be requested.