The PCIe4 CDa is a PCI Express 4-lane interface that enables fast DMA and synchronous I/O to transfer differential (LVDS or RS422) data between an external device and a host computer.
The PCIe4 CDa provides one Altera Arria II GX FPGA (EP2AGX45D) which combines PCIe functionality (for DMA) and UI functionality (for I/O).The buffers are integrated FIFOs for input and output. Current FPGA configuration options include…
- Standard DMA: One 16- or 32-bit parallel channel, or sixteen synchronous serial channels; or
- Optional low-latency DMA: One 16-bit parallel channel. Observed data rates on the PCIe connector are up to 700 MBytes per second. Observed data rates on the I/O connector are 150 Mbits per second:
- 1 parallel channel = 600 MB/s total for 32-bit, or 300 MB/s total for 16-bit
- 1 serial channel = 150 Mb/s The hardware protocol is synchronous: all data and control signals are sampled by a clock transmitted along with them. This sample clock can be generated by the DMA interface, the user device, or both.For custom designs, EDT allows access to the source VHDL in the FPGA.
System must have a PCI Express bus (4, 8, or 16 lanes) that is not dedicated to display use only. See system requirements.