- PCIe (Gen3) x8 interface with one 40G QSFP+ and up to two 10G SFP/+s
- Data formats: 1/10/40GbE, OC3/12/48/192 (STM1/4/16/64), OTU1/2/2e/2f
- FPGA + DMA: One user-programmable Altera Stratix V 5SGX (A3, A5, A7, or A9), configurable for up to 16 independent DMA channels
- DRAM (DDR3): Two independent 4 GB blocks
- EDT intellectual property for 10GbE PCS and PMA layers, SONET/SDH framing, demultiplexing, and G.709 framing
- Time code input: 1 pps or IRIG-B, with user-configurable output
The PCIe8 G3 S5-40G is a fast, versatile PCI Express (PCIe, Gen3) x8 interface with one 40G QSFP+ and up to two 10G SFP/+ ports. It supports 1/10/40GbE, OC3/12/48/192 (STM1/4/16/64), or OTU1/2/2e/2f.
Each port of the PCIe8 G3 S5-40G links to the FPGA for serialization / deserialization (SERDES) and clock recovery. Each port has its own reference clock, programmable for 10–210 MHz.
The single FPGA is an Altera Stratix V GX (A3, A5, A7, or A9) with access to two independent 4 GB blocks of DRAM (DDR3), which can act as data buffers. The FPGA provides up to 16 independent DMA channels via EDT FPGA configuration files.
A time code input (1 pps or IRIG‑B) also is included, with an option for either DB9 or BNC cabling.
EDT FPGA configuration files are included to support 1GbE and 10GbE at the PHY layer; OC3/12/48/192 and OTU1/2/2e/2f (raw, framed, framed and descrambled); and demultiplexing. Custom files can be requested.
Datasheet PCIe8 G3 S5-40G