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EDT PCI CDa Xilinx Spartan IIE | LVDS or RS-422



  • PCI interface for high-speed DMA (one or sixteen channels) and synchronous
  • RS422 or LVDS I/O (one, two, eight, or sixteen channels)
  • Supports one, two, eight, or sixteen channels of differential data:
    - One 16-bit parallel;
    - Two 8-bit parallel (full duplex);
    - Eight synchronous serial with data valid; or
    - Sixteen synchronous serial
  • FPGA: One user-programmable Xilinx Spartan IIE
    - Standard XC2S100E for one or two data channels; or
    - Optional XC2S600E for eight or sixteen data channels
  • I/O: RS422 or LVDS
  • Buffers: Integrated FIFOs for input and output
  • Clock: 33 or 66 MHz, 3- or 5-volt PCI-capable
  • Data rates:
    - With one DMA channel, 210 MBytes per second
    - With sixteen DMA channels, 70 Mbits per second per channel

The PCI CDa board provides one high-speed 16-bit parallel channel or an optional 16 synchronous serial channel between an external device and a PCI local bus computer (or optional 16-channel* synchronous serial interface). The device interface uses LVDS- or RS422-compatible driver/receivers connected to a field-programmable gate array (FPGA).

The PCI CDa uses direct memory access (DMA) and asynchronous I/O to achieve transfer rates to or from memory of up to 210 megabytes per second (observed). The hardware protocol is synchronous; that is, all data and control signals are sampled with a clock transmitted along with the data and control signals. This clock may be generated by the DMA interface the user device or both. All signals are differential using LVDS (or optional RS422) specifications.

The PCI CDa includes a versatile, straightforward protocol but optional customer-specific protocols may be developed.

* For 16-channel capability, the CDa must have an optional Xilinx XC2S600e installed and use the ssd16io bitfile.


The system must have a PCI or PCI-X bus, 66 MHz or faster (33 MHz will work but at reduced data rates). See system requirements.

Datasheet PCI CDa

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