EDT Combo E1/T1, E3/T3, ECL interface

Features

16 E1/T1 line interfaces
Four E3/T3 line interfaces
16 ECL differential inputs/outputs
Large Xilinx FPGA provided by EDT PCIe8 LX main board
Two large synchronous static memory banks or one memory bank up to 1 GB (also provided by mainboard – see details below)
LVDS External clock that can be used to synchronize the output data
16 independent DMA channels to host memory
Fast transfers using a 66 MHz 32-bit PCI

Applications

Telecommunications network monitoring
Telecommunications switching

The Combo Mezzanine board pairs with a PCI / PCIe, EDT PCIe8 LX main board. The board pair supports the processing of large amounts of telecom serial or ECL data for complex, user-defined applications. The high-speed 16-channel DMA controller allows flexible access to host memory. The main board supplies the DMA, memory, and programmable FPGA resources (see ordering options below); EDT provides FPGA configuration files.

Specifications

PCI/PCIe bus compliance related to the mainboard.
UI FPGA (main board)	PCI SS: Xilinx XCV1000E or optional XCV600E, XCV2000E PCI GS: Xilinx XC2VP50 or optional XC2VP70 User definable LED Debug connector, 20-pin .100″ x .100″ square pins, two rows
Memory main board
Local	PCI SS: Two 256K x 36-bit word synchronous static RAM or optional no RAM, 512K x 36-bit word RAM, or 1M x 36-bit word RAM PCI GS: 1M x 36-bit word synchronous static RAM or optional 2M x 36-bit word RAM (with XC2VP70)
Dynamic	PCI GS: 200-pin SODIMM socket for optional DDR memory module. Up to 1 gigabyte.

External Connectors	High-density 68-pin AMP™ connector (part number 787169-7) High-density 15-pin AMP™ receptacle (part number 748390-5)
User Interface Xilinx	PCI SS: XCV1000E or optional XCV600E, XCV2000E PCI GS: XC2VP50 or optional XC2VP70 User definable LED Debug connector, 20-pin .100" x .100" square pins, two rows
Local Memory	PCI SS: Two 256K x 36-bit word synchronous static RAM or optional no RAM, 512K x 36-bit word RAM, or 1M x 36-bit word RAM PCI GS: 1M x 36-bit word synchronous static RAM or optional 2M x 36-bit word RAM (with XC2VP70)
ECL	16 differential ECL signals; input or output in groups of four Standard ECL signal levels terminated through 50 ohms to -2V
E3/T3	Transformer coupled Four independent E3/T3 interfaces Jumpers select input/output or both on eight differential connector pins 75-ohm coaxial cable over 1100 feet at speeds up to 51.84 MB per second Compliant with ANSI T1.102-1993, Telcordia GR-499-CORE and G.823 for jitter tolerance B3ZS or HDB3 encoder/decoder
E1/T1	16 independent input/output E1/T1 interfaces Jumpers select input/output or both on 16 differential connector pins 1.544 MB per second (T1), 2.048 MB per second (E1) Waveforms meet G.703 and T1.102 specifications Exceeds transmit return loss specification ETSI ETS-300166 Jitter attenuation Transmit return loss exceeds ETSI ETS 300166 HDB3 or B8Zs encoder/decoder Analog/Digital and remote loopback
Physical Number of Slots Dimensions	1 4.2" x 6.6"
Environmental
Temperature	Operating: 0 to 44 °C Non-operating: -40 to 70 °C Heat Output: TBD
Humidity	Operating: 1% to 90% non-condensing at 40° C Non-operating: 95% non-condensing at 45° C
Power	2 amps at 5V

Software

Device drivers for Windows and Linux are included with the purchase of the board. Contact us about other operating systems.

Support

EDT provides several levels of customer support, from phone consultation to custom design of hardware, firmware, or software, at hourly rates. Technical support is also provided through the Support section of the EDT website.

Third-party support

Technisys, Inc. provides a family of interface panels designed to provide an easy and economical method of interfacing to the EDT Combo Mezzanine and other EDT products. See their website, www.tsys-inc.com.

Ordering

Ordering options are listed below. To order, contact Parhelia B.V. Be sure to specify which cable will be needed (if any).

Mainboard options

PCIe8 LX / FX / SX main board – for options, contact Parhelia B.V.

User Guide

Feel free to request a quote